Turnkey Designs- Silicon Engineering

Exascale Processor

Top Processor Foundry : 10nm
  • Partitioned into ~98 Unique Blocks
  • 3.2 GHz Target Frequency
  • 3-levels of hierarchical implementation
  • Team Size: 35 – PD / STA / IR / PV
  • Time Frame: 10-months
Challenges
  • Channel-less design
  • Clock Tree OCV induced timing issues
  • Top level timing closure / Merged Mode Timing
Custom Solutions
  • Data path / Clock Branch Visualizer
  • Path Group based top -> Sub-chip violation Analyzer

APU

TSMC N7 HPC
  • Hierarchical Channel Less Design
  • ~160 Unique Blocks
  • Targeting Multi-GHz Frequency
  • Owned 25% of complex blocks
  • Team size: 30 engaged over 9-months
Challenges
  • AON Cell Clustering in ONO Regions
  • Context Aware Cell Placement
Custom Solutions
  • Custom Repeater-flop placement flow
  • SI Violations fixing solution

AI Accelerator

TSMC 16nm FF
  • RAP Technology
  • 1.0 GHz Frequency
  • Complete RTL2GDSII ownership
Challenges
  • Hierarchical timing closure
  • Crossbar Implementation
  • Full Chip Timing ECOs
Methodology /Custom Solutions
  • ILM based clock-skew balancing
  • Scripted hierarchical Hold Fix solution

Server Processor SOC

  • XSP (3D- XPoint)
  • Test Bench Development
  • Functional Verification using UVM

AI Accelerator (SOC)

  • SOC Verification
  • IP Verification
  • Gate Level Simulation

Ethernet MAC (400G)

  • Test Bench Development
  • Bus Functional Model Development
  • Functional Verification and Environment Development using UVM and System Verilog

Camera Application

  • Test plan Development
  • MBIST, Functional BIST Implementation
  • ATPG and Test Compression
  • Modular Scan

AI Accelerator (SOC)

  • Chip Level DFT Architecture Design
  • Clock Structure
  • BIST, MBIST, JTAG, DFT Constraints, ATPG
  • Tester Output Validation
  • Zero DPPM Assurance

Server Processor

  • ATPG Generation and Compression for over 130 Blocks
  • Scan Insertion and Stitching
  • Block to SOC Level Pattern Conversion
  • Post Silicon Validation